The invention generally relates to an information processing apparatus including a unique, external memory unit having a programmable processor embodied therein. More particularly, the invention relates to a removable, external memory unit having a program memory storing a program to be executed in part by a host processing system, e.g., a video game system, and in part by a programmable microprocessor designed to enhance the high speed graphics processing capabilities of the host system.
Prior art video game machines having an 8-bit microprocessor and an associated display processing subsystem embodied in a video game control deck typically generate graphics by prestoring characters in a game cartridge in the form of 8-bit by 8-bit matrices and by building a screen display using various programmable combinations of these prestored characters. Such prior art video game systems typically have the capability of moving the entire display background as well as a number of player-controlled xe2x80x9cmoving objectsxe2x80x9d or xe2x80x9cspritesxe2x80x9d.
Such prior art systems do not have the capability of practically implementing video games which include moving objects made up of combinations of polygons which must be manipulated, e.g., rotated, and xe2x80x9credrawnxe2x80x9d f or each frame. The prior art 8-bit processor and associated display processing circuitry in such systems are not capable, for example, of performing the calculations required to effectively rotate three-dimensional, polygon-based objects or to appropriately scale such rotating objects to generate 3-D type special effects. The present inventors have recognized that sophisticated graphics require updating the screen on a pixel-by-pixel basis and performing complex mathematics on a real time basis. Such prior art character based video game machines are not capable of performing such tasks.
The prior art 8-bit video game machines also can not effectively perform other graphics techniques which require rapidly updating the screen on a pixel-by-pixel basis. For example, such systems can not effectively map an object onto a displayed polygon which is part of yet another displayed object (hereinafter referred to as xe2x80x9ctexture mappingxe2x80x9d) in three-dimensional space.
In an effort to improve the graphics capabilities over prior art 8-bit machines, video game systems have been designed using more powerful 16-bit processors. Such 16-bit processors provide the video game system with a mechanism for performing the mathematics required for more sophisticated graphics. Such systems, for example, permit more sophisticated color generation and better graphics resolution. Such 16-bit video game machines are character-based systems which permit the implementation of a wide range of video games that can be pre-drawn into character-based or sprite graphics. Such 16-bit video game systems also permit the movement of multiple colored background planes at high speeds with moving objects disposed in back, or in front, of such planes.
However, such prior art 16-bit video game machines do not permit the practical implementation of advanced video games having 3-D type special effects which display sophisticated objects made up of polygons that must change during each frame. For example, games which require many fully rotating objects or sprites that must be enlarged and/or reduced on a frame-by-frame basis are not practically realizable in such prior art character-based 16-bit machines. The inventors have recognized that, in order to effectively implement such games involving fully rotating and scaled, polygon-based objects, it is necessary to draw the edges of polygons and fill in such polygon-based objects with appropriate data on a pixel-by-pixel basis. Such tasks, which must be done on a pixel-by-pixel basis, consume a great deal of processing time.
In the prior art, removable game cartridges have been modified to improve game sophistication by permitting existing processors to address a larger program memory address space than the existing number of address lines associated with the host microprocessor would otherwise permit. For example, such prior art 8-bit systems have utilized game cartridges including multi-memory controller chips which perform memory bank switching and other additional functions. Such memory bank switching related chips, however, are not capable of enabling the video game system to do high speed graphics processing of the nature described above.
The present invention addresses the above-described problems in the prior art by providing a unique, fully programmable, graphics microprocessor which is designed to be embodied in a removable external memory unit for connection with a host information processing system. In an exemplary embodiment described herein, the present invention is embodied in a video game system including a host video game system and a video game cartridge housing the graphics microprocessor.
The graphics microprocessor and the video game system described herein include many unique and advantageous features, some of which are summarized below.
In accordance with the present invention, a unique graphics processor is pluggably connected to a host microprocessor. In order to maximize processing speed, the graphics processor may operate in parallel with the host microprocessor. In one exemplary embodiment, the game cartridge in which the graphics coprocessor resides also includes a read-only memory (ROM) and a random-access memory (RAM).
The graphics coprocessor of the present invention arbitrates memory transactions between its own needs and data fetches from the host microprocessor. The processor is capable of executing programs simultaneously with the host microprocessor to permit high speed processing, heretofore not achievable in prior art video game systems.
The graphics coprocessor of the present invention operates in conjunction with a three bus architecture embodied on the game cartridge which permits effective utilization of the RAM and ROM cartridge memories by optimizing the ability of both the host and cartridge processors to efficiently use such memory devices.
The fully user programmable graphics coprocessor of the present invention includes a unique instruction set which is designed to permit high speed processing. The instruction set is designed to efficiently implement arithmetic operations associated with 3-D graphics and, for example, includes special instructions executed by dedicated hardware for plotting individual pixels in the host video game system""s character mapped display.
Many of the instructions in the instruction set are capable of being executed in one machine cycle and are designed to be stored in one byte of program ROM. However, the instructions may be made more powerful through the use of special purpose, prefix instructions.
The instruction set includes unique pixel-based instructions which, from the programmer""s point of view, create a xe2x80x9cvirtualxe2x80x9d bit map by permitting the addressing of individual pixelsxe2x80x94even though the host system is character based. The pixel data is converted on the fly by the graphics processor to character data of a format typically utilized by the host character based 16-bit machine. Thus, for example, although the programmer may use a unique xe2x80x9cPLOTxe2x80x9d instruction to plot a pixel, when related data is read to RAM, the data is converted to a character-based format which the 16 bit host machine is able to utilize. Special purpose pixel plotting hardware executes this instruction to efficiently permit high speed 3-D type graphics to be implemented.
The graphics coprocessor of the present invention also includes a unique xe2x80x9cCACHExe2x80x9d instruction and a cache memory mechanism which permit program instructions stored in the program ROM to be executed at high speed by the graphics coprocessor from cache RAM. The CACHE instruction permits a programmer to automatically initiate the execution of program out of the graphics coprocessor internal cache RAM by delineating that part of the program which is to be executed at high speed.
The instruction set also includes special purpose instructions designed to aid in programming the graphic techniques required to implement video games having sophisticated 3-D type features. Such instructions include the above-described pixel PLOT instruction and a MERGE instruction, designed to permit merging of sprite data stored in different registers to more efficiently permit rotation of displayed objects or and texture mapping.
Special purpose instructions permit the buffering of data to permit parallel processing by the host microprocessor and the graphics coprocessor of the present invention. For example, a special purpose instruction is utilized for enhancing processing speeds, to compensate for the relatively slow access time ROMs utilized in game cartridges. In this regard, the graphics processor uses an instruction in which any reference to a predetermined general register (e.g., a register R14 in the exemplary embodiment) automatically initiates a data fetch from ROM. While such ROM accesses are taking place, other code may be executed. Some cycles later, the fetched data will be available. However, in the meantime, the processor did not have to wait for such data but rather was able to accomplish other tasks thereby allowing for very fast executing code to be written.
In order to efficiently handle subroutine linkage, the graphics coprocessor of the present invention also includes a LINK instruction which operates to load the address of the instruction to be executed after the subroutine has been completed into the program counter R15 at such time of completion.
The instruction set includes a RAM store-back instruction. In accordance with this instruction, after data is read from RAM and an operation is performed on such data, a RAM controller within the graphics coprocessor initiates an updated data store-back operation at the appropriate last used RAM address. This one cycle store back instruction may be advantageously used to efficiently update blocks of data.
The graphics coprocessor of the present invention also includes instructions which automatically permit the reading or writing from RAM using the least significant byte followed by the most significant byte. This mechanism serves as a programming aid in providing compatibility with data stored of either format without having to perform any data transposition.
The graphics processor of the present invention may be set to a number of different plotting modes by modifying an internal processor status register. Such modes include a dithering mode which enables the generation of programmable shading effects, where each alternate pixel contains a different color. Another selectable mode permits high and low nibble selection for colors to permit two sprites to be stored in memory in a space which would otherwise be taken up by one sprite.
The present invention includes many unique hardware features. For example, the graphics coprocessor includes special purpose plotting circuitry which includes enhanced pixel data buffering through the use of on-chip RAM. Such data buffering minimizes the amount of read or write transactions to the external data RAM and enhances the speed at which displayed polygons may be xe2x80x9cfilledxe2x80x9d with appropriate data.
In addition to the read buffering feature which is initiated upon any access to register R14 as described above, the graphics coprocessor of the present invention also includes write buffering features in which data to be written to the game cartridge RAM is buffered to enable the central processing of the Mario chip to execute other instructions as rapidly as possible.
The graphics coprocessor of the present invention also includes sixteen registers, R0-R15, which are accessible to both the graphics processor and the host processing system. Register R0 is a default register which need not be expressly identified in an instruction and which serves as an accumulator. Register R15 serves as a program counter. Register R14 is the register referred to above which, if accessed, automatically initiates a data fetch from ROM. Special prefix instructions may be used to define the source and/or destination registers. The graphics coprocessor of the present invention interacts with the host coprocessor such that the graphics coprocessor""s registers are accessible to the host processor.
A unique three bus architecture associated with the graphics coprocessor permits a high degree of parallelism. The 3 buses include the host processor bus, a ROM bus, and a RAM bus. These buses are physically separate and may be used simultaneously. Each bus includes address lines, data lines, and control lines. The host processor bus includes address lines, data lines, and control lines which supply a wide range of signals required within the graphics coprocessor. The graphics processor of the present invention using this bus architecture may execute programs from either the program ROM, external RAM or its own internal cache RAM.
The graphics coprocessor interfaces with the host microprocessor using various arbitration modes. In this regard, by loading a logical xe2x80x9c1xe2x80x9d in a predetermined graphics processor status register position, an arbitration mode is set by the host processor to indicate that the host processor has given up access to the game cartridge""s ROM and RAM.
The present inventors have recognized that, even under circumstances where the host processor has given up access to a ROM and RAM by appropriately setting the status register, interrupts may nevertheless occur where the host processor may initiate a ROM access to fetch an address of a routine for handling such an interrupt. Under such circumstances, the graphics processor operates to provide the host microprocessor with a working RAM address instead of the program ROM address, causing the host processor to access its own internal working RAM. This technique keeps the host processor from addressing the program ROM at the time when the graphics coprocessor is executing from program ROM.
When the host processor needs to access the cartridge RAM, the graphics coprocessor status register is set such that the graphics coprocessor is unable to access RAM, thereby enabling the host processor to access whatever information is required from RAM and to thereafter switch the graphics coprocessor to a state where access to RAM is possible. However, it is desirable for the coprocessor to utilize ROM and RAM on the cartridge to the maximum extent possible due to its faster processing speed.
The graphics coprocessor of the present invention is designed to efficiently transfer pixel information loaded in the character data RAM to the host processor video RAM for display. The video RAM is not however, directly accessible to the graphics coprocessor through any cartridge bus. Such transfer must occur through using the direct memory access (DMA) circuits of the host processor.
The graphics coprocessor of the present invention receives several clock signals from the host information processing system. Timing within the graphics coprocessor is driven by one of the these clocks.
As an optional feature of the present invention, circuitry within the graphics coprocessor permits the processor to be reconfigured to account for future modifications depending upon the state of signals received via output address lines which are used as configuration setting input lines immediately after power-on reset. The values of option setting resistors coupled to these address lines are read by the graphics coprocessor. These signals are used to define, for example, the type of RAM chip that is being utilized with the graphics processor, e.g., static RAM or dynamic RAM.
These and other aspects and advantages of the present invention will become better understood from the following detailed description of the present exemplary embodiment of the present invention when taken in conjunction with the accompanying drawings of which: